Integrated circuit (IC) process and package limitations associated with decreasing minimum feature size are making it increasingly difficult to retain prior pin pad (pin box) spacing (pitch). For example, single exposure and single etch (1P1E) photolithography techniques limit pin box pitch to 800 nm for 5 specified pins, but 5 input/output (I/O) pins electrically coupled to a static random access memory (SRAM) multiplexer one (MUX1) memory cell in some newer standard cell libraries only allows for 450 nm to 720 nm total space for pin boxes, which is not sufficient for 5 I/O pins.
While 1P1E photolithography techniques limit pin box pitch to 800 nm for 5 pins, double exposure and double etch (2P2E) photolithography techniques limit pin box pitch to 635 nm for 5 pins. Although 2P2E pitch at 635 nm is preferable to 1P1E pitch at 800 nm in terms of space required, 2P2E pin boxes have additional electrical limitations in addition to requiring too great a pitch for many standard cell applications.